lesson
The NAND Gate Set-Reset (SR) Latch and Active-Low Inputs
Analyse the feedback operation, active-low inputs (S-bar and R-bar), and truth table of a cross-coupled NAND gate SR latch.
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Latches, Flip-Flops, and Sequential Timing
11th Grade · Technology · UK A-Level
7 lessons
Goal
Analyse and design cross-coupled NAND SR latches and edge-triggered D-type flip-flops while evaluating propagation delays and timing diagrams.
7 lessons
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- The NAND Gate Set-Reset (SR) Latch and Active-Low InputsYou are here
- 2SR Latch Metastability, Invalid States, and Switch Debounce CircuitsPremiumUp next
- 3D-Type Flip-Flops: Clock, Data, Set, and Reset PinsNot started yet
- 4Transition Gates: Generating Clock Pulses from Edge TransitionsNot started yet
- 5Propagation Delay, Setup Time, and Hold Time in Sequential SystemsNot started yet
- 6Constructing and Interpreting Timing Diagrams for Sequential CircuitsNot started yet
- 7D-Type Flip-Flops as Toggle Divide-by-Two Frequency DividersNot started yet
Learning standards covered
ELEC-10.1General Certificate of Education Advanced Level (UK A-Level) · Electronics · 11th Gradea Set-Reset (SR) latch based on NAND gates, including the design and description of the action
ELEC-10.3General Certificate of Education Advanced Level (UK A-Level) · Electronics · 11th Gradethe construction and use of timing diagrams to explain the operation of sequential logic circuits