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Imagine designing an analogue interval timer that needs a precise 15 nF15\text{ nF} capacitance to achieve an exact 1.0 s1.0\text{ s} delay, but your parts kit only contains standard 10 nF10\text{ nF} components.
By connecting capacitors in networks, we can engineer custom capacitance values and customize how charge flows through timing circuits.

Parallel Capacitor Networks

When capacitors are placed in parallel, both terminals of every capacitor connect directly across the same voltage source, meaning the voltage (VV) across each component is identical.
Placing capacitors side-by-side effectively joins their plate surface areas together, creating a larger total surface area to store electric charge.
Because total charge is conserved, the total charge QtotalQ_{\text{total}} stored by the bank equals the sum of the individual charges: Qtotal=Q1+Q2+⋯+QnQ_{\text{total}} = Q_1 + Q_2 + \dots + Q_n.
Substituting the fundamental capacitance relationship Q=C×VQ = C \times V gives:
CpV=C1V+C2V+⋯+CnVC_p V = C_1 V + C_2 V + \dots + C_n V
Dividing both sides by the common voltage VV yields the equivalent parallel capacitance formula: Cp=C1+C2+⋯+CnC_p = C_1 + C_2 + \dots + C_n
If you connect a 10 nF10\text{ nF} capacitor and a 4.7 nF4.7\text{ nF} capacitor in parallel, the total equivalent capacitance is simply 10 nF+4.7 nF=14.7 nF10\text{ nF} + 4.7\text{ nF} = 14.7\text{ nF}.
What happens if we wire capacitors end-to-end in a single line instead of side-by-side?

Series Capacitor Networks