lesson
Updated 6 days ago · 1 view
Every digital stopwatch, frequency divider, and CPU instruction sequencer relies on counting pulses. But how do you make a circuit count when it only knows how to store single bits?
A D-type flip-flop stores a single binary state (0 or 1) and updates its output Q on a clock pulse. If you route the inverted output Qˉ back into data input D, the flip-flop inverts its output on every active clock edge, creating a divide-by-2 toggle circuit.
📊Interactive diagram
What happens if we take that halved frequency output and feed it directly into the clock input of a second flip-flop?
Cascading for Up and Down Counting
In an asynchronous counter (also called a ripple counter), only the first stage connects to the master clock. Each subsequent stage is clocked by the output of the previous stage, rippling the transition through the chain like a line of falling dominoes.
With standard negative-edge (falling-edge) triggered flip-flops, connecting clock input CLKn+1 to Qn creates a binary up-counter (0002→1112). Connecting CLKn+1 to Qˉn (or reading from Qˉ) creates a down-counter (1112→0002).
📊Interactive diagram
A 3-bit counter naturally cycles through 23=8 states (0 through 7). But what if your system needs a standard base-10 decade counter or a base-6 second counter for a digital clock?
Modulo-N Truncation
The modulo (or MOD number) is the total number of unique states a counter visits before repeating. To truncate a counter so it counts from 0 up to N−1 (a MOD-N counter), we detect the unwanted state N and instantly force all flip-flops back to 0.
Most flip-flops have active-low asynchronous clear inputs (CLR or RESET), which immediately force Q=0 when brought low (0 V). We feed the outputs that are logic 1 in state N into a NAND gate, connecting its output to every flip-flop's CLR pin.
📊Interactive diagram